1. Field of the Invention
The present invention generally relates to a semiconductor memory device utilized in a semiconductor integrated circuit, and more specifically relates to layouts of data reading lines in such semiconductor memory devices.
2. Description of the Related Art
In semiconductor memory devices for reading and writing data, generally, when reading out data stored in a memory cell, its small current is amplified by a sense amplifier in order to output the data to the outside.
FIG. 12 is a schematic block diagram of an example of conventional semiconductor memory device. Only one input terminal DI and one output terminal DO are shown in FIG. 12 for simplicity.
In FIG. 12, data read out from a memory cell array 101 are inputted via a bit line pair BL and a data line pair CL to a sense amplifier 103.
The sense amplifier 103 detects a very small potential difference on the bit line pair BL and amplifies it. A data element outputted from the sense amplifier 103 passes through a selection gate 104 comprising an NMOS transistor and is latched in a latch circuit 105. The latch circuit 105 holds the data even after the operation completion of the sense amplifier 103. The data latched in the latch circuit 105 are outputted by an output buffer 106 to the outside at an output terminal DO. During a writing operation, based on an input data element inputted at an input terminal DI to an input circuit 107, a write buffer 108 drives the bit line pair BL having a large load capacity, and writes the data element into a selected memory cell in the memory sell array 101.
FIG. 13 is a schematic block diagram of another example of a conventional semiconductor memory device. In the semiconductor memory device shown in FIG. 13, data provided from a desired selection gate among a plurality of selection gates are outputted to the outside through an output terminal DO. Parts shown in FIG. 13 the same as or similar to parts shown in FIG. 12 are assigned the same reference numbers as those in FIG. 12. The semiconductor memory device shown in FIG. 13 is normally used when separating a large capacity memory cell array 101 into several blocks.
In the semiconductor memory device shown
FIG. 13, similar to the device shown FIG. 12, sense amplifiers SA0˜SAn detect a very small potential difference on bit line pairs BL and amplify it. One of the data elements outputted from the sense amplifiers SA0˜SAn is selected by selection gates SG0˜SGn, and latched in a latch circuit 105. The latched data element is the one of the selected block among a plurality of blocks having the plurality of sense amplifiers.
In the actual circuit layouts of the semiconductor memory devices shown in FIGS. 12 and 13, circuits within and outside of the memory cell array 101 have to be dense in order to reduce cell sizes. There are many varieties of signal lines laid adjacent to the output data line IDO. For example, FIG. 14 shows an example layout of such data lines. An input data line IDI for writing data and an internal control signal line CKL for transmitting an internal synchronization signal ICK are laid adjacent to an output data line IDO for reading out data. The internal synchronization signal ICK controls the whole internal circuit in the semiconductor memory device. In another example, the output data line IDO is laid adjacent to wirings between a column gate 102 and sense amplifiers.
In such dense layouts, surrounding signals create a bad effect as noise. Especially, the output data line IDO is an important bus determining the operation speed, but it has a problem in that it is intolerant of noise. For example, the bit line pair BL transmits a very small electric current, and therefore is easily affected by noise generated by surrounding circuit operations. As a result, data output from the sense amplifiers may become incorrect.
In a case where data speed is prioritized in a fast memory and the like, a latch circuit 105 has weak data holding ability. If noise occurs during the holding period of the latch circuit 105, the output data line IDO is easily affected by the noise, and the data stored in the latch circuit 105 may be inverted. And if noise invades the output data line IDO, it erroneously drives the large output buffer 106 and may induce further power supply noise.
Japanese Patent Laid-Open Publication 11-134872 discloses one scheme regarding signal line layout for reducing cross talk noise where output data badly affect an external signal line. In the layout, the external signal line is disposed between one signal line for transmitting non-inverted output data and another signal line for transmitting inverted output data in order to reduce the influence by noise generated by the output data line. In this case, transition periods of the output data line are noise sources.
Another scheme is known (e.g., Japanese Patent Laid-Open Publications 7-211069 and 2001-167572), in which adjacent signal lines are changed at a regular interval in order to reduce coupling noise capacities between signal lines. This scheme can separate some couples that would make noise due to signal level variations, and can reduce the noise.
Recently the coupling noise has become a serious problem as device sizes become smaller and smaller. FIG. 15 is a graph illustrating an example of noise influence on the output data line IDO shown in FIG. 14. As seen in FIG. 15, a signal on the output data line IDO has coupling noise due to the variation in a signal on the input data line IDI. After closing the selection gate 104, the data on the output data line IDO are maintained by the latch circuit 105 only. Under this condition, when a data element to be written is inputted to the input terminal DI, the level of the input data line IDI changes and then may influence the input data line IDO, which drives the output buffer 106, resulting in further power supply noise.
When a data element to be written is inputted during the data holding period of the latch circuit 105, the output data line IDO may have a coupling noise as explained above. If both signals on the input data line IDI and on the internal control signal line CKL similarly change simultaneously, a signal on the output data line IDO is influenced and may be inverted, and then the data held in the latch circuit 105 may be broken by inversion. Therefore it is desirable to solve this noise problem.
The input signal to the sense amplifier also may be subject to noise influence. For example, in a case where the internal control signal line CKL transmitting a large signal such as an internal synchronization clock signal ICK is disposed in parallel with wiring between the sense amplifier 103 and the column gate 102 as shown in FIG. 12, the potential on the bit line pair BL is varied due to coupling noise. Especially, even if one bit line of the bit line pair BL is influenced by such noise, the sense amplifier 103 may malfunction or be delayed.
In the prior example shown in FIG. 13, similar to FIG. 12, if writing lines such as the output data line IDO or the data line pairs CL receive noise, malfunction may occur. Especially, when a split-word line system is employed, the data line pairs CL have long lengths. If the memory cell array 101 is separated into blocks as discussed in relation to FIG. 13, the sense amplifiers SA0˜SAn have to be disposed adjacent to corresponding memory cell blocks. Accordingly, the output data line IDO becomes longer, and therefore a signal transmitted on the output data line IDO becomes more sensitive to a coupling noise.
In the split-word line system, since a plurality of bits are treated as one data element, a plurality of data lines are laid in parallel with each other. Accordingly, a conventional method for shielding the data lines with power supply lines requires a larger layout size. There is another conventional method in which the sense amplifiers do not read out while noise source circuits are operating. There is a further conventional method in which noise source circuits do not operate while data are being read out from the memory cell array. These methods however require additional controlling circuits and may degrade the performance of the semiconductor memory device itself.
Further there is another conventional method in which while data are being read out from the sense amplifiers, clocked inverters employed in the latch circuit 105 are prohibited from operating. In this method, it is necessary to match the inverter's timing with the selection gates and therefore to add a controlling circuit for controlling the timing.